Sg2524 pdf

Timing Resistor, R T. Timing Capacitor, C T. The oscillator controls the frequency of the. SG - SG Pratical values of C T fall between 0. This results in a frequency range typically. The output pulse of oscillator is used as a blank-. This pulse width is con-. If small values of C T are. If still greater dead-time is required, it. This can easily be done with the circuit be-. Figure 6. When an external clock is desired, a clock pulse.

The impedance to. In this. If two more SG regulators are to be operated. V REF. The output of the error amplifier shares a common input to the comparator with the current-limiting and shut-down circuitry and can be overridden by signals from either of these inputs. This common point is pinned out externally via the COMP pin, which can be employed to either control the gain of the error amplifier or to compensate it. In addition, the COMP pin can be used to provide additional control to the regulator.

Practical values of RT fall between 1. This results in a frequency range typically from Hz to kHz. This pulse duration is controlled by the value of CT as shown in Figure 5. In this configuration, RTCT must be selected for a clock period slightly greater than that of the external clock. The oscillator programmed for the minimum clock period is the master from which all the other SGs operate. In this configuration, however, the input voltage is limited to a maximum of 6 V. Error-Amplifier Bias Circuits error amplifier The error amplifier is a differential-input transconductance amplifier.

The output is available for dc gain control or ac phase compensation. Refer to Figure 3 for data. Since most output filters introduce one or more additional poles at frequencies below Hz, which is the pole of the uncompensated amplifier, introduction of a zero to cancel one of the output filter poles is desirable. Caution should be taken to ensure the —1-V limit is not exceeded by either input, otherwise, damage to the device may result. Foldback current limiting can be provided with the network shown in Figure 7.

The current-limit schematic is shown in Figure 8. Each transistor has antisaturation circuitry that limits the current through that transistor to a maximum of mA for fast response. They can be segregated into three basic categories: D Capacitor-diode-coupled voltage multipliers D Inductor-capacitor-implemented single-ended circuits D Transformer-coupled circuits Examples of these categories are shown in Figures 9, 10, and 11, respectively.

Detailed diagrams of specific applications are shown in Figures 12— All linear dimensions are in inches millimeters. This device can be used for switching regulators of either polarity, transformer coupled DC to DC converters, transformerless voltage doublers and polarity converters, as well as other power applications.

By matching the base-emitter voltages of Q1 and Q2, and assuming a negligible voltage drop across R1: C. This requires sensing in the ground or return line of the power supply. Also precautions should be taken to not turn on the parasitic substrate diode of the integrated circuit, even under transient conditions.

A Schottky clamp diode at Pin 5 may be required in some configurations to achieve this. A second factor to consider is that the response time is relatively slow.

The current limit amplifier is internally compensated by R 1 , C 1 , and Q1, resulting in a roll-off pole at approximately Hz. A third factor to consider is the bias current of the C. Sense pins. Since the gain of this circuit is relatively low 42 dB , there is a transition region as the current limit amplifier takes over pulse width control from the error amplifier.

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